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TC55V040AFT-55,-70 2003-08-06 1/11 toshiba mos digital integrat ed circuit silicon gate cmos 524,288-word by 8-bit full cmos static ram description the TC55V040AFT is a 4,194,304-bit static random access memory (sram) organized as 524,288 words by 8 bits. fabricated using toshiba's cmos silicon gate process technology, this devi ce operates from a single 2.3 to 3.6 v power supply. advanced circuit technology provides both high speed and low power at an operating current of 3 ma/mhz and a minimum cycle time of 55 ns. it is automatically placed in low-power mode at 0.5 a standby current (at v dd = 3 v, ta = 25c, maximum) when chip enable ( ce1 ) is asserted high or (ce2) is asserted low. there are three control inputs. ce1 and ce2 are used to select the device and for data retention control, and output enable ( oe ) provides fast memory access. this device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. and, with a guaranteed operating extreme temperature range of ? 40 to 85c, the TC55V040AFT can be used in environments exhibiting extreme temperature conditions. the TC55V040AFT is available in normal and reverse pinout plastic 40-pin thin-small-outline package (tsop). features ? low-power dissipation operating: 10.8 mw/mhz (typical) ? single power supply voltage of 2.3 to 3.6 v ? power down features using ce1 and ce2 ? data retention supply voltage of 1.5 to 3.6 v ? direct ttl compatibility for all inputs and outputs ? wide operating temperature range of ? 40 to 85c ? standby current (maximum): 3.6 v 7 a 3.0 v 5 a pin assignment (top view) 40 pin tsop pin names a0~a18 address inputs 1 ce , ce2 chip enable r/w read/write control oe output enable i/o1~i/o8 data inputs/outputs v dd power gnd ground nc no connection pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pin name a16 a15 a14 a13 a12 a11 a9 a8 r/w ce2 nc nc a18 a7 a6 a5 a4 a3 a2 a1 pin no. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pin name a0 ce1 gnd oe i/o1 i/o2 i/o3 i/o4 nc v dd v dd i/o5 i/o6 i/o7 i/o8 a10 nc nc gnd a17 ? access times (maximum): TC55V040AFT -55 -70 access time 55 ns 70 ns 1 ce access time 55 ns 70 ns ce2 access time 55 ns 70 ns oe access time 30 ns 35 ns ? package: tsop ? 40-p-1014-0.50 (aft) (weight: 0.32 g typ) (normal) 21 40 20 1
TC55V040AFT-55,-70 2003-08-06 2/11 block diagram operating mode mode 1 ce ce2 oe r/w i/o1~i/o8 power read l h l h output i ddo write l h * l input i ddo output deselect l h h h high-z i ddo h * * * high-z i dds standby * l * * high-z i dds * = don't care h = logic high l = logic low maximum ratings symbol rating value unit v dd power supply voltage ? 0.3~4.6 v v in input voltage ? 0.3 * ~4.6 v v i/o input/output voltage ? 0.5~v dd + 0.5 v p d power dissipation 0.6 w t solder soldering temperature (10s) 260 c t stg storage temperature ? 55~150 c t opr operating temperature ? 40~85 c * : ? 3.0 v when measured at a pulse width of 50ns column address buffer a5 i/o1 memory cell array 2,048 256 8 (4,194,304) column address decoder column adderss register sense amp a6 a7 a8 a9 a12 a11 a13 a14 ce v dd gnd ce a4 a18 a2 a0 a1 a17 a3 a10a15a16 row address decoder row address buffer row address register i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 data control clock generator 8 ce 1 ce r/w oe ce2
TC55V040AFT-55,-70 2003-08-06 3/11 dc recommended operating conditions (ta = ? 40 to 85c) 2.3 v~3.6 v symbol parameter min typ max unit v dd power supply voltage 2.3 3.0 3.6 v v ih input high voltage 2.2 ? v dd + 0.3 v v il input low voltage ? 0.3 * ? v dd 0.22 v v dh data retention supply voltage 1.5 ? 3.6 v * : ? 3.0 v when measured at a pulse width of 50 ns dc characteristics (ta = ? 40 to 85c, v dd = 2.3 to 3.6 v) symbol parameter test condition min typ max unit i il input leakage current v in = 0 v~v dd ? ? 1.0 a i oh output high current v oh = v dd ? 0.5 v ? 0.5 ? ? ma i ol output low current v ol = 0.4 v 2.1 ? ? ma i lo output leakage current 1 ce = v ih or ce2 = v il or r/w = v il or oe = v ih , v out = 0 v~v dd ? ? 1.0 a 55 ns ? ? 60 70 ns ? ? 50 l ddo1 1 ce = v il and ce2 = v ih and r/w = v ih and i out = 0 ma, other input = v ih /v il v dd = 3 v 10% t cycle 1 s ? ? 10 ma 55 ns ? ? 55 70 ns ? ? 45 l ddo2 operating current 1 ce = 0.2 v and ce2 = v dd ? 0.2 v and r/w = v dd ? 0.2 v, i out = 0 ma, other input = v dd ? 0.2 v/0.2 v v dd = 3 v 10% t cycle 1 s ? ? 5 ma i dds1 ce = v ih or ce2 = v il ? ? 2 ma ta = 25c ? ? 0.6 v dd = 3 v 10% ta = ? 40~85c ? ? 6 ta = 25c ? ? 0.7 v dd = 3.3 v 0.3 v ta = ? 40~85c ? ? 7 ta = 25c ? 0.05 0.5 ta = ? 40~40c ? ? 1 i dds2 (note) standby current 1 ce = v dd ? 0.2 v or ce2 = 0.2 v v dd = 1.5 v~3.6 v v dd = 3.0 v ta = ? 40~85c ? ? 5 a note: in standby mode with 1 ce v dd ? 0.2 v, these limits are assured for the condition ce2 v dd ? 0.2 v or ce2 0.2 v. capacitance (ta = 25c, f = 1 mhz) symbol parameter test condition max unit c in input capacitance v in = gnd 10 pf c out output capacitance v out = gnd 10 pf note: this parameter is periodically sampled and is not 100% tested.
TC55V040AFT-55,-70 2003-08-06 4/11 ac characteristics and operating conditions (ta = ? 40 to 85c, v dd = 2.7 to 3.6 v) read cycle TC55V040AFT -55 -70 symbol parameter min max min max unit t rc read cycle time 55 ? 70 ? t acc address access time ? 55 ? 70 t co1 chip enable( 1 ce ) access time ? 55 ? 70 t co2 chip enable(ce2) access time ? 55 ? 70 t oe output enable access time ? 30 ? 35 t coe chip enable low to output active 5 ? 5 ? t oee output enable low to output active 0 ? 0 ? t od chip enable high to output high-z ? 25 ? 30 t odo output enable high to output high-z ? 25 ? 30 t oh output data hold time 10 ? 10 ? ns write cycle TC55V040AFT -55 -70 symbol parameter min max min max unit t wc write cycle time 55 ? 70 ? t wp write pulse width 45 ? 50 ? t cw chip enable to end of write 50 ? 60 ? t as address setup time 0 ? 0 ? t wr write recovery time 0 ? 0 ? t odw r/w low to output high-z ? 25 ? 30 t oew r/w high to output active 0 ? 0 ? t ds data setup time 25 ? 30 ? t dh data hold time 0 ? 0 ? ns ac test conditions parameter test condition output load 30 pf + 1 ttl gate input pulse level 0.4 v, 2.4 v timing measurements v dd 0.5 reference level v dd 0.5 t r , t f 5 ns
TC55V040AFT-55,-70 2003-08-06 5/11 ac characteristics and operating conditions (ta = ? 40 to 85c, v dd = 2.3 to 3.6 v) read cycle TC55V040AFT -55 -70 symbol parameter min max min max unit t rc read cycle time 70 ? 85 ? t acc address access time ? 70 ? 85 t co1 chip enable( 1 ce ) access time ? 70 ? 85 t co2 chip enable(ce2) access time ? 70 ? 85 t oe output enable access time ? 35 ? 45 t coe chip enable low to output active 5 ? 5 ? t oee output enable low to output active 0 ? 0 ? t od chip enable high to output high-z ? 30 ? 35 t odo output enable high to output high-z ? 30 ? 35 t oh output data hold time 10 ? 10 ? ns write cycle TC55V040AFT -55 -70 symbol parameter min max min max unit t wc write cycle time 70 ? 85 ? t wp write pulse width 50 ? 55 ? t cw chip enable to end of write 60 ? 70 ? t as address setup time 0 ? 0 ? t wr write recovery time 0 ? 0 ? t odw r/w low to output high-z ? 30 ? 35 t oew r/w high to output active 0 ? 0 ? t ds data setup time 30 ? 35 ? t dh data hold time 0 ? 0 ? ns ac test conditions parameter test condition output load 30 pf + 1 ttl gate input pulse level v dd ? 0.2 v, 0.2 v timing measurements v dd 0.5 reference level v dd 0.5 t r , t f 5 ns
TC55V040AFT-55,-70 2003-08-06 6/11 timing diagrams read cycle (see note 1) write cycle 1 (r/w controlled) (see note 4) address r/w ce2 d out t as t cw t wr valid data in t odw d in t wp t ds t dh t oew (see note 2) hi-z t cw t wc (see note 3) (see note 5) 1 ce (see note 5) address ce2 d out t rc t acc t oh t co2 t oee t odo hi-z hi-z t co1 1 ce oe t od t oe t coe valid data out indeterminate
TC55V040AFT-55,-70 2003-08-06 7/11 write cycle 2 ( controlled) (see note 4) write cycle 3 (ce2 controlled) (see note 4) ce1 1 ce ce2 address r/w t wc t as t wr t wp d out t cw valid data in t odw d in t ds t dh t coe hi-z hi-z t cw (see note 5) address r/w t wc t as t wr t wp 1 ce d out t cw valid data in t odw d in t ds t dh t coe hi-z hi-z t cw ce2 (see note 5)
TC55V040AFT-55,-70 2003-08-06 8/11 note: (1) r/w remains high for the read cycle. (2) if ce1 goes low(or ce2 goes high) coincident with or after r/w goes low, the outputs will remain at high impedance. (3) if ce1 goes high(or ce2 goes low) coincident with or before r/w goes high, the outputs will remain at high impedance. (4) if oe is high during the write cycle, the outputs will remain at high impedance. (5) because i/o signals may be in the output state at th is time, input signals of reverse polarity must not be applied. data retention characteristics ( ta = ? 40 to 85c ) symbol parameter min typ max unit v dh data retention supply voltage 1.5 ? 3.6 v ta = ? 40~40c ? ? 1 v dh = 3.0 v ta = ? 40~85c ? ? 5 i dds2 standby current v dh = 3.6 v ta = ? 40~85c ? ? 7 a t cdr chip deselect to data retention mode time 0 ? ? ns t r recovery time t rc (see note) ? ? ns note: read cycle time controlled data retention mode (see note 1) ce2 controlled data retention mode (see note 3) ce1 2.7 v gnd v ih data retention mode t r (see note 2) (see note 2) t cdr v dd ? 0.2 v 1 ce v dd v dd v dd 2.7 v gnd v il data retention mode t r t cdr 0.2 v v ih ce2 v dd
TC55V040AFT-55,-70 2003-08-06 9/11 note: (1) in ce1 controlled data retention mode, minimum standby current mode is entered when ce2 0.2 v or ce2 v dd ? 0.2 v. (2) when ce1 is operating at the v ih level (2.2v), the operating current is given by i dds1 during the transition of v dd from 3.6 to 2.4v. (3) in ce2 controlled data retention mode, mi nimum standby current mode is entered when ce2 0.2 v.
TC55V040AFT-55,-70 2003-08-06 10/11 package dimensions weight: 0.32 g (typ)
TC55V040AFT-55,-70 2003-08-06 11/11 ? the information contained herein is subject to change without notice. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba produc ts, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshiba products specific ations. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semicon ductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are inte nded for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunc tion or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control in struments, airplane or spaceship instruments, transportation instruments, traffic signa l instruments, combusti on control instruments, medical instruments, all types of safety devices, etc .. unintended usage of toshiba products listed in this document shall be made at th e customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the down stream products which ar e prohibited to be produced and sold, under any law and regulations. 030619eb a restrictions on product use

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